According to Chaoming Zhang et al, “Built-In Test of RF Mixers Using RF Amplitude Detectors”, 2007 IEEE Proceedings of the 8th International Symposium on Quality Electronic Design, 26-28 Mar. 2007, PP. 404˜409, it is disclosed, as the way of reducing manufacturing test time of an RF circuit built in SoC (System on Chip) or SiP (System in Package) and the cost thereof, to connect an input terminal of an RF detector with an output of an RF mixer.
The RF detector includes a pseudo-differential pair composed of two N-channel MOS transistors to detect an output from the RF mixer. Between the drain and gate of each N-channel MOS transistor, a resistance for biasing a gate voltage of the transistor is connected.
The sources of the two N-channel MOS transistors are connected to the earth potential commonly. The drains of the two N-channel MOS transistors are connected to a P-channel MOS bias current mirror composed commonly. Two capacitances connected to the gates of the two N-channel MOS transistors serve to block DC current which affects a detecting operation. To the drains of the two N-channel MOS transistors, an output capacitance for holding an output voltage is connected.
Further, JP 2006-099810 discloses a sub-carrier detection circuit for detecting the presence or absence of a non-contact IC-card in a read/write device which performs reading from and writing into a non-contact IC-card.
In this sub-carrier detection circuit, when a sub-carrier signal from a coil antenna of a non-contact IC-card is applied to a base of a detection transistor, which has been supplied with a fixed bias voltage resulting from voltage division of a source voltage, a half-wave rectification output signal is formed by a resistance and a capacitance connected in parallel in association with an emitter of the detection transistor.